John Janowski
Senior Staff Engineer at Intel Corporation
Based in Iselin, United States
7-day free trial · no credit card
Seniority
Staff
Department
Engineering
Location
Iselin
Industry
Semiconductor Manufacturing
Company size
110K
Contact information
Reveal John's email and phone
Direct contact data is gated. Sign up and reveal. You only pay for verified records.
j•••••••@intel.com
Phone
5 credits+1 ••• •••• ••••
You only pay for valid records. Bounced emails and disconnected numbers cost nothing.
Background
About John Janowski
over 14 years of digital I.C. physical design experience. Also known as (AKA) layout designer. AKA place and route engineer. AKA I.C. CAD designer. AKA semiconductor physical designer. AKA structural design engineer AKA Back-End semiconductor design engineer. Specialty: place and route using Synopsys' ICC2 or Fusion Compiler; From synthesis through layout verification, timing ECOs and back-end physical checks. Layout verification using Mentor Graphic's Calibre and Synopsys's IC Validator Static timing analysis using Primetime Synthesis using Design Compiler, or Fusion Compiler VCLP low power checks top or subsystem level floor planning
Decision-makers
Other people at Intel Corporation
Build a list of verified contacts at Intel Corporation
Free for 7 days · 50 credits · no card · only pay for verified records.
Reach more buyers like John
250M+ professionals with verified email and phone. You only pay for records that actually verify.
7-day trial · no credit card · cancel anytime