Jonathan Raymond

Background

About Jonathan Raymond

Logic design engineer working on Power microprocessors. Involved in architecture, design, verification, debug (simulation and hardware), synthesis, timing closure, and test. Have worked on both 7xx series Power designs, gaming system processors, and P series. I have been involved in all phases of design from early block level simulation through first hardware prototype manufacturing debug, early user system bringup/debug, and final product manufacturing yield improvement. I have also worked on ASIC SOC designs implementing various bus/memory controller IP cores, high speed serial links, Infiniband Link Layer cores, and Ethernet Phy cores. I have experience in many industry and proprietary design tools including: Synopsis Design Compiler, PrimeTime static timing analysis, Synopsis VCS, Cadence Incisive simulator, Mentor Graphics Modelsim, IBM synthesis tools, IBM Einstimer, IBM ASIC layout/floorplanning, Verilog and VHDL design languages, Perl, TCL, C, C++.