Jorge Moran

Hsio Sr Physical Design Engineer at Intel Corporation

Based in Austin, United States

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Seniority

Staff

Department

Engineering

Location

Austin

Industry

Semiconductor Manufacturing

Company size

110K

Contact information

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Email

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j•••••••@intel.com

Phone

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Background

About Jorge Moran

M.Sc. on Electrical Engineering, specialty on VLSI, detail oriented and risk taking engineer with 15+ years of industrial experience in preSi design (10+ on Back End). Strong focus on process/methodology/automation improvement- 4+ years of experience in all aspects of physical implementation from RTL synthesis to GDS (tape in) on 14 and 10nm process for mixed signal IOs, such as QPI and PCIe-DMI (2nd and 3rd generation). Experience on Floor planning, timing budgeting, Timing convergence, ETM generation/ quality verification for multi voltage/frequency designs - 2+ years of experience on Reliability verification- 6+ years of experience in fully custom blocks.

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