Justin Arul

Background

About Justin Arul

Generated ARM CMN-S3AE interconnect through socrates and integrated the block into top level wrapper.• Executed synthesis and achieved timing closure with optimized SDC constraints.• Performed RTL to RTL, RTL-to-gate and gate to map Logic Equivalence Checking (LEC) and debugged RTL/netlist integration issues related to clocking, reset, and connectivity.• Designed and integrated ARM CoreSight IP for system-level debug, trace, and monitoring.• Achieved clean lint, CDC, and RDC signoff using industry-standard static verification tools.• Developed RTL register blocks and maintained RDLs for configuration and control.• Collaborated with high-speed USB IP teams on complex multi-version SoC designs.• Improved RTL quality, performance, and power using SpyGlass, Questa CDC/RDC, FCelab, and Power Artist.• Optimized power performance using Power Artist, implementing techniques like clock gatingin early design stages.• Verified functionality through waveform debug and system-level test scenarios, also familiar with AMD design flows (DJ, BIA, RDL).