Kapil Seth
Technical DV Lead at Intel Corporation
Based in Santa Clara, United States
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Seniority
Other
Department
Other
Location
Santa Clara
Industry
Semiconductor Manufacturing
Company size
110K
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k•••••••@intel.com
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Background
About Kapil Seth
Experienced SoC design verification Lead Engineer with a demonstrated history of working in the computer hardware industry. Strong engineering professional skills in Semiconductors RTL design Unit/System level verification FPGA/Silicon validation Perl Debugging. Verification/Validation experience in leading AI systems next gen multi die multi core data center server products specially security technologies like MKTME SGX and TDX etc. Experience in writing unit level testbenches from scratch in system verilog (plane SV/UVM/VMM) TB architecture transactors and peripheral device models. System/Cluster level verification of ARM based SOCs. Good understanding of Peripheral IPs like Memory controller SDMMC NAND flash controller NOR controller QSPI DDR SPI Slave I2C UART MIPIHSI etc. System BUS protocols like AXI AHB and APB. Video Engine modules like BSEV TFE etc.
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