Karthik V.

Background

About Karthik V.

I’m a graduate of CSU Fresno with solid hands-on experience across the RTL-to-GDSII flow. I’ve worked at the 2nm, 3nm, 7nm, 28nm, and 45nm nodes on scan insertion, ATPG, physical synthesis, place and route, timing closure, and physical verification. I’ve used tools like Synopsys DC, FC, ICC2, PrimeTime, TetraMax, Cadence Innovus, Virtuoso, and Tessent FastScan for scan compression and fault grading. I focus on delivering clean netlist, realistic timing, closing STA, and ensuring designs are both physically and logically correct before tape-out. I make sure the design can play in any weather — stressing it across all corners and extremes to guarantee rock-solid silicon. I’ve built and debugged memory controllers and network interface logic, and I enjoy working on real-world challenges — whether it’s timing noise, IR drop, DRC/LVS issues, or test coverage — and making sure the design gets out the door clean.