Kiran Kumar Jallada

Background

About Kiran Kumar Jallada

Experience in ASIC Design Verification of multiple SOCs and Processors. I've enjoyed developing testbench from scratch and also jump into the existing complex verification environment quickly. Extensive knowledge of ASIC design flow like functional verification, formal verification, low power verification, emulation, DFD, DFT-JTAG and GLS. Expertise in architecting and implementing self-generating and self-checking simulation verification environment to reach functional coverage goals using random/directed stimulus for a given IP/SOC. Accomplished tape-outs without major bugs without compromising on the deadlines by leading team ensuring timely completion of the set objectives. Interfaced with the Design & Architecture team for quick responses. Expertise in understanding the criticality of issues and implementing apt resolutions. Reduced client issues by executing new verification strategies and tools and which successfully gauged various bugs in the design. Evaluated and scrutinized customer issues and enhanced verification environment to avoid recurrence of issues. I am looking for most challenging and complex SOC verification roles where my strong technical skills are utilized.