Luong Ngo
Wireless Digital Sr Staff Engineer at Qualcomm
Based in San Diego, United States
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Seniority
Other
Department
Other
Location
San Diego
Industry
Semiconductor Manufacturing
Company size
53K
Contact information
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l•••••••@qualcomm.com
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Background
About Luong Ngo
Overview Of Working Experience:_Comprehensive design experience as Asic designer. Most of my projects were large, complex systems requiring maximum performance. I have taken projects from rough spec to production._Comprehensive experience at ASIC and FPGA board level. Systems were partitioned and implemented at ASIC and board level as needed. Experience on validating system concept._Proven experience and track records in managing design complexity through careful choice of architecture, design and testing techniques.*Power management IC Digital design Module specification and architecture definition; Design lead and project management; Chip integration, Digital module design and mixed mode; Project lead or leading role experience; Backend sign-off knowledge; Familiar with digital design flow; Experience of collaboration with software and system engineer *SOC experience from spec to tape-out. Architecture design and RTL implementation; System bus and mobile peripheral designs; Familiar with digital IC design, DFT, Experienced in SoC architecture. Experienced in chip integration; Experience with External Memory Interface design; Experience with system verification; Experience with analog/digital interface design.*Asic Experience Experience on 802.11-baseband wireless LANs. Comprehensive knowledge with the high bandwidth multiple flows hardware Mac (medium access control layer), good understanding of physical layer architecture. Successfully brought low-level documents to one-pass chip product._ Responsible for implementation of new designs, which based on standard base-band GSM chipset, successfully brought projects specification into products. Contributed to the hardware definition requirements, particularly in terms of technical solutions._Proven track records of tape-out of high complexity large ASIC designs. Understand timing constraints and perform DFT insertions, ATPG generation on top level for large ASIC.
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