Majd Eid

Background

About Majd Eid

I Worked on multiple Integrated Chip projects for Automotive and Space communication application in process nodes from 40nm- 180nm. The blocks designed include: High voltage power management circuits, Temperature monitor, High speed differential data convertors, High bandwidth differential filters and variable gain amplifiers, low- distortion buffer drivers and Phase locked loop system. A summary is below: o COA Collins aerospace: A MEMS oscillator PLL chip. I worked on behavioral modelling of a Voltage Controlled oscillator (VCO) using Verilog-A for system level simulations. o Ensilica “HAWK” Solenoid Controller ASIC: H-Bridge Solenoid controller ASIC to be used in electronically controlled cars’ suspension for the automotive company Jaguar Land Rover. The chip was fabricated in TSMC 180nm technology and operates on voltage range from 5V-36V. My role was to design the Power management circuits in the chip, which include a Bandgap circuit and LDO regulator to supply the internal circuitries with stable 1.8V with 20mA current sourcing capability. I also designed a temperature monitor circuit for fault detection. o CASSIS (Connected Automotive Satellite Service Integrated System): A versatile multi-channel, Ka frequency band, beamforming transceiver chip for phased arrays with four inputs and outputs per chip fabricated in GF 40nm technology. The mmWave chip was developed as part of European Space Agency’s Advanced Research in Telecommunications Systems (ARTES) project and the CASSIS project, which is led by the UK Satellite Applications Catapult (UKSAC). My role was to a design a differential cascaded signal chain consisting of a variable gain amplifier with programmable gain from 2dB-16dB, followed by a 3rd order low-pass filter with programmable cut-off frequency form 10MHz- 320MHz and a low-distortion buffer output driver capable of delivering 2.5mA current to 50ohm differential load. I also designed an 8-bit differential SAR ADC with sampling rate of 10MSPS to monitor and measure internal signals. o Leonardo Project: A PLL system that was originally designed for the aerospace and defence company Leonardo SpA. The project was not fabricated in silicone however it was fully designed and simulated in ST65nm technology. My role was to design the PLL system, including the majority of the sub blocks within such as Voltage Controlled Oscillator (VCO), Charge pump (CP), Phase frequency detector (PFD) and the biasing block. The PLL was designed to operate at temperature range from -193C to 27C and can produce output clock frequency from 100MHz-1GHz.