Mandar Kulkarni

Background

About Mandar Kulkarni

20+ years of experience in the chip design, building and leading teams across multiple geographies to successfully deliver multiple SoC's at various process nodes. • Chip lead for multiple generations of Networking, Server, 5G SoC's.• Built a fully self-sufficient physical design team at the California Design Center at Cavium.• Extensive experience in staffing, making backend project schedules, resolving resource conflicts to enable parallel execution of multiple programs.• Interfaced with multiple vendors for IP selection for SerDes, DDR, standard cell libraries.• Lead various product feasibility studies to provide correct power/area/performance metrics for successful product specification across various technology nodes.• Highly Experienced in:o Physical Design Asic flows for rtl logic synthesis (DCT/DCG), place and route (ICC/ICC2/Innovus), Static Timing Analysis (PrimeTime), power estimation (PTPX), EMIR (Redhawk), Formal Equivalency (Formality), signal integrity and final physical verification checks (LVS/DRC with caliber).o Implementing various low power design techniques such as fine-grain clock gating, power islands, leakage recovery. o Chip Lead for SoC designs in 28nm, 14/16nm, 5nm process nodes.o The entire SoC design life-cycle for front end feasibility/design to tape-out. o Semiconductor product development, standard cell library, memory compiler IP selection