Manish Murthy

Background

About Manish Murthy

Specializing in Synthesis, Timing Closure, and Static Timing Analysis With nearly 2 years of hands-on experience in block and full-chip level synthesis, logical equivalence check (LEC), and static timing analysis (STA), I bring a strong skill set in ensuring timing closure and design optimization across various technology nodes including 90nm, 28nm, and 4nm. Proficient in utilizing Synopsys synthesis tools and adept at Perl and TCL scripting, I have a proven track record of handling timing constraints and resolving timing violations efficiently. Currently serving as an Engineer I at Capgemini Engineering, I am entrusted with synthesizing RTL code, logical optimization, constraints definition, and performing static timing analysis to ensure design integrity and meet timing requirements. Additionally, I specialize in timing ECOs and LEC modeling, demonstrating my ability to troubleshoot and enhance design robustness. In my previous role as a Physical Design Engineer at Capgemini Engineering, I contributed to the success of projects involving 90nm technology chips, utilizing Oasys tool for synthesis and Nitro tool for physical design. My responsibilities included floor planning, macro placement, and conducting timing reports to ensure design specifications are met.