Manoj Kulkarni

Background

About Manoj Kulkarni

IO/Analog circuit design professional with 12 yrs of experience. Have recently worked on GDDR and HBM PHYs.Expertise in low power Rx front end for HBMExpertise in low power, low DNL-INL CMOS based delay lines intended for long ranges and high precision for (LP)DDR applicationsExpertise in DDR IO circuit design viz. AFEs of Rx & Tx, Delay lines, Vref and Calib. I have dealt with delivery of DDR libraries.Experience in full path analysis of 10Gbps serial interface from GCD to MCD on a silicon interposer. Ownership was to estimate the non-idealities (jitter contributions), look for the weak points in the design and come up with available eye opening at the Rx sampler.Have designed GPIO libraries like LVCMOS, LVDS, I2C, etcHave worked on MIPI Mphy PWM Rx, USB FSTx.Experience in Verilog, timing and IBIS modeling.Exposure to variety of process nodes from 180nm down to 5FF with emphasis on aging, self heating, device reliability, etc.Good understanding of ESD and signal integrity and their implications on circuit design. Proven track record of effective project planning and risk management with effective mitigation and contingency plans.Core interest in understanding the non idealities in the design and budgeting them.Keen on game changing aspects of design like biasing strategies, slew control mechanisms, cross corner compensation for tighter control on specs.Favourite circuits include high speed level up shifters, high speed Rx AFE, best in class PPA delay lines. Multiple executive spotlight awards for execution excellence and contribution to the team.