Mantesh Math
Analog and Digital Layout Design Engineer at Karmic Design Private Ltd
Based in Bijapur, India
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Seniority
Staff
Department
Other
Location
Bijapur
Industry
Semiconductors
Company size
236
Contact information
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m•••••••@karmic.co.in
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Background
About Mantesh Math
Memory,Digital and Analog layout engineer at SiyaCon Technology Pvt, Ltd. Experience in Memory,Digital and Analog layout design with a good knowledge in DRC, LVS, Antenna PEX checks. Layout Editing tool: Cadence Virtuoso Layout Editor, Synopsys Custom Compiler. IC Verification Tools: Assura, Calibre, PVS Process node: 5nm,7nm,12nm,22nm,45nm,90nm and 180nm. Simulation Tool: LTSPICE, NG-SPICE, Cadence NC-sim Simulator. Programming Languages: Basics of Verilog, C programming. Application Software: MS-Office. Libre Office Layout responsibility: Floor Planning, Matching devices, Placement and Routing. Blocks Handled in Analog Layout: Level shifter, Single stage Differential amplifier, Resistor trimmer circuit for different levels of output for LDO, Folded cascode differential amplifier. Low-Dropout Voltage Regulator(LDO). BGR, PLL. Blocks Handled in Memory Layout: SRAM Array organization, GDP(IO)-Pre-charge, Write Driver, MUX, Sense Amp, LDP(IO)- Latch's. Blocks Handled in STD-CELL Layout: Basic Gates, AOI, OAI, Flip-Flops. Parasitic Extraction: RC extraction. Programming Languages: Unix Shell, Perl,Python, Skill.
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