Mark Haas

Background

About Mark Haas

Admirable experience working as an IC Physical/ Mask Design Senior Engineer, with previous work experience in Senior level PCB Design. Experienced at working in diverse environments with many circuit designers from multiple design center locations including travel to international and national locations. Lead designer experience; floor planning, creating top level designs, delegating cell and block layouts and creating or updating a program schedule to support a team. Techniques used are matching devices & placement of dummies interdigitation, quad coupling, base layer and metal fill, use of shielding critical net as well as guard ring shielding when necessary. Driven with proven ability to ‘do what it takes’ to complete a project efficiently to achieve highest quality outcomes. Excellent communication skills with ability to work successfully in either an independent role or a lead role; experience as a Program Manager for Eaton Corporation designs. Subject Matter Expert with proven experience mentoring new hires and team members. Primary application trainer for co-workers and peers; chosen to attend multiple applications training sessions. Twelve years of experience designing custom analog hierarchical layouts using Cadence Virtuoso XL to assemble pcells for analog, memory, and supporting digital cells. CMOS down to sub 65nm, BiCMOS & Bipolar technologies. Design Applications: Cadence Virtuoso XL, Cadence, Mentor Verification S/W: Hercules, Assura, Calibre and Diva DRC, Extract and LVS Database Management Synchronicity Operating Systems: UNIX with tshell and custom script programming to complete layouts. Project Management: Microsoft Word, Excel, PowerPoint, and Project,