Mark Pirner
Asic Design Verification Engineer at Qualcomm
Based in Toronto, Canada
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Seniority
Staff
Department
Engineering
Location
Toronto
Industry
Semiconductor Manufacturing
Company size
53K
Contact information
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m•••••••@qualcomm.com
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Background
About Mark Pirner
I am going into my junior year in Computer Engineering at the University of Toronto, specializing in digital systems design and parallel programming. Last summer I worked as a Software Engineering Intern at Entegra, and I currently work as a Design Verification Engineering Intern at Qualcomm and concurrently work as Planning Lead for UofT's Formula Racing Team’s autonomous vehicle. Driven by a passion for continuous learning, I have completed several courses focused on Computer Architecture, hands-on FPGA development, Circuit Analysis, and embedded software. I am proficient in Verilog, VHDL, TCL, C, C++, C#, and have experience designing digital systems on FPGA and creating back-end systems for real time and other applications. I am enthusiastic about applying my skills in hardware design to tackle challenges and foster innovation in the field. I am eager to contribute to impactful projects and collaborate with teams that share my dedication to learning and advancing technology.
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