Mary L.
Sr Mask Layout Designer at Analog Bits
Based in San Jose, United States
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Seniority
Staff
Department
Engineering
Location
San Jose
Industry
Semiconductor Manufacturing
Company size
64
Contact information
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m•••••••@analogbits.com
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Background
About Mary L.
Experience Leading the layout team to work on PLLs and SerDes - SerDes Samsung FinFET 5, 7, 8 Samsung 28 & 32, TSMC FinFET 14 & 16, TSMC 28, 40 & 65 - PLL/Testchip TSMC/Samsung FinFET 5, 7, 14 & 16 also 28 & 40 · Experience in setup, floor planning, schedule planning, building cell level, block level, and top level · Work on top level signal and power routing · Run LVS, DRC, extractions, ERC, and soft checks using Calibre, Mentor Graphics Tool · Responsible for leading the team and release projects
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