Michael Huebner

Background

About Michael Huebner

Research- Adaptive run-time system with intelligent allocation for dynamically reconfigurable function patterns and optimized interface topologies - Dynamic and partial reconfiguration of Xilinx FPGAs - Network-On-Chip Architectures - Robust and resilience for cyberphysical systems Activities Program Chair der ReCoSoc 2008 Program Chair des International Workshop on Reconfigurable Computing Education (RC-Education) 2008 (http://helios.informatik.uni-kl.de/RCeducation08/) Publicity Chair der International Conference on Reconfigurable Computing and FPGAs (RECONFIG Program Chair des International Workshop on Reconfigurable Computing Education (RC-Education) 2007 (http://helios.informatik.uni-kl.de/RCeducation07/) Local Chair des Computer Society Annual Symposium on VLSI (ISVLSI 2006) Program Commitee Member: The International Conference on Field-Programmable Logic, Reconfigurable Computing and Applications (FPL), Computer Society Annual Symposium on VLSI (ISVLSI), Reconfigurable Architecture Workshop (RAW), Reconfigurable Co-Centric SoCs (ReCoSoc), HiPEACRC, Programm Chair des International Workshop on Reconfigurable Computing Education (RC-Education), IET Irish Signals and Systems Conference Publicity Chair at FPL 2009 Program Chair of ReCoSo 2010, Karlsruhe Germany Program Chair of DASIP 2011, Tampere Finnland Workshop organizer at DAC 2011:"DAC Workshop on Multiprocessor System on Chip for Cyber Physical Systems: Programmability, Run-Time Support and Hardware Platforms for High Performance Embedded Applications" Member of the ISVLSI Steering Committee Program Chair for DASIP 2011, Program Chair for RAW 2012, Program Chair for FPL 2014 Program Chair for AHS 2014, Workshop Chair ViPES 2014, Program Chair ReConFig 2014 Actual over 250 publications in international journals and conference proceedings. Specialties: Reconfigurable Technologies Application specific, run time adaptive processors