Michel Rohner

Background

About Michel Rohner

As individual contributor and also team leader, has delivered innovative solutions through several large and technically challenging projects. Technical management and implementation of architecture, hardware and software design and verification of ASIC/FPGA/DSP/SOC/GPU based products. Detailed design, coding and troubleshooting skills in Hardware, Firmware and Software system development. Consistently produced results that exceeded performance and cost goals (video image quality, compact designs, fast and accurate computations/simulations, inventive algorithms, thorough debugging and excellent documentation). AREAS OF EXPERTISE Provided complete system solutions with hardware design, verification and troubleshooting- Patents: Several patents related to high-speed hardware and 3D graphics - Languages: C/C++, MFC, Open CL, Open GL, Verilog, HTML, PHP - OS and Scipt: RTOS: Windows, Linux/Unix/Gnu, uCos, Perl, Python, TCL - RTL design/verification: Verilog, SystemVerilog, UVM, Specman, Vivado, Verdi, ModelSim, NCVerilog - Transaction Level Models: Coded TLMs in C++ to prove design, generate test vectors, speed up debugging- Components: Xilinx FPGA (Virtex, Artix, Kintex, Zynq), ARM Proc, DSP - ASICs Design & Verif Produced 3 ASICs (3D graphics chips and Quad TV Decoder/Encoder)- 3D Graphics Many years of 2D and 3D graphics accelerators & ASIC design experience- 3D Architect Lead architect for several 3D graphics system for High Speed 3D Rendering- Video and TV Encoder/Decoder, Scalers and Digital Filters for HDTV, NTSC and PAL - Interfaces SERDES, RS232, JTAG, I2C, SPI, SMBus, PCIe- Hands on Debugging Excellent troubleshooting skills (System level, Gate level, Scope, Log Analyz.)- Documentation Excellent Design documentation and comprehensive test procedures