Milad Maleki

Background

About Milad Maleki

3+ years of experience in Logic Design (Verilog/VHDL), Synthesis, Timing analysis, Verification using SystemVerilog, C/C++, Java, Python, Perl, Tk/Tcl for SoC/ASIC/FPGA. 5+ years of Academic/Research experience in design and software development for SoC, ASIC and FPGA. Experience in cross-layer design, performance modeling and optimization using simulation, statistical data analysis and dynamic algorithms. Expertise in parallel programing and accelerator code and algorithm emulation and optimization with FPGA using OpenCL, HDL programming and SystemC. Expertise/experience in algorithm design, development and debug of C++ STL/Java codes, Flex & Bison parsers using CVS/RCS and gdb/jdb. Extensive experience in applying low power design techniques in various RTL levels, Integration of power and clock gating, multi-voltage domain, multi-Vth cells, Razor logic and algorithm level techniques. Experience in hardware security, Hardware Trojan design and detection; Cryptographic Cipher design. Expertise in low power RTL design and verification using Cadence/Synopsys/Mentor Graphics tools.