Mukesh Saha

Background

About Mukesh Saha

Hello Connection, Welcome to my profile! I am a VLSI Design and Verification professional with over 2 years of experience specializing in IP and Processor verification. Currently, I am actively involved in debugging issues related to Google RISC-V DV GitHub. My expertise lies in Digital Electronics, and I possess strong knowledge in Verilog, SystemVerilog, and UVM. In my career, I have successfully developed various components like packet, generator, driver, monitor, and scoreboard in a SystemVerilog environment. Additionally, I have hands-on experience in creating sequence, sequencer, monitor, driver, and agent within a UVM environment. I take pride in my proficiency in developing test benches in both UVM and SystemVerilog environments. Functional Coverage is an area I excel in, and I have a solid understanding of APB and AHB protocols. My knowledge extends to the Linux environment, providing me with a well-rounded skill set in the field. Furthermore, I am well-versed in RISC-V architecture, particularly in RV32/64IMAFDC variants. I am adept at crafting RISC-V assembly-level tests, targeting various architecture and microarchitecture features. Additionally, I have knowledge of random generators and reference models for processor verification, along with a deep understanding of RISC-V ISA and computer architecture. To complement my verification work, I possess good scripting skills in Shell and Python, enabling me to automate tasks efficiently. Overall, my professional experience has equipped me with comprehensive skills in VLSI Design and Verification, making me a valuable asset in the industry. Verification: Manage development of testplans, tests, System Verilog/UVM based testbenches, regressions, functional and code coverage goals Thank you for visiting my profile! Feel free to reach out to me for any further inquiries or opportunities.