Nagesh Thambu
Associate Director
Based in Bengaluru, India
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Bengaluru
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About Nagesh Thambu
 WORK PROFILE: ● A post-graduate in VLSI Design and having 15.10 years of extensive experience in SOC Sub-System & IP Micro-Architecture Design and Verification. ● Hands-on experience on complete ASIC development cycle which includes Arch/Micro-Architecture RTL Design Front end flow execution Lint CDC LEC Timing Constraints/synthesis STA DFT UPF GLS FECO Boot/SW deliverables & Silicon Validation. ● Experience in executing complete design cycles for SoCs. Successfully executed 4-SOCs as Functional lead at Samsung. ● Worked closely with cross-functional teams for overall IP & SoC architecture definition and implementation. ● Expertise in power domain partitioning for complex low power IP/SOC. ● Experience in handling a team of 12 people and responsible for their deliverables as a Technical Lead and grooming them in terms of understanding their expectations work assignments and mentoring them as their manager. ● Experience in interacting with EDA vendors on a timely basis to discuss tool related issues and flow enhancements to achieve efficiency in execution and have improvement in QoR. AREA(s) of EXPERTISE ● Developing Micro architecture and RTL coding using Verilog HDL & System Verilog. ● Lint CDC UPF Synthesis STA LEC ECO’s GLS Power Aware-RTL/GLS. ● IP-Packaging Integration netlist generation and register management based on IP-XACT. ● Netlist Simulation. Functional verification and gate level simulation SKILLS ( Tools / Languages / Methodology) ● Languages: Verilog VHDL and System Verilog. ● Scripting languages: Perl Python ● CDC & Linting Tools: Leda Spyglass ● Synthesis & STA Timing Tools: Design Compile FC & PTsi. ● Equuivalence Checking & ECO’s: Formality DC ICC2 & FC. ● Simulation Tools: VCS Modelsim NC launch T-Spice. ● Debug tool: Verdi Nwave. ● IP-XACT Tool: Magillem. ● FPGA Tools: XILINX ALTERA. ● Layout Tools: L-Edit Cadence Virtuoso. ● Protocols: USB 2.0 UFS PCIe I2C UART & SPI and AXI AHB APB
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