Nitheesh Appala
Asic Hardware Design Engineer at Abacus Semiconductor Corporation
Based in Portland, United States
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Seniority
Staff
Department
Engineering
Location
Portland
Industry
Semiconductors
Company size
21
Contact information
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n•••••••@abacus-semi.com
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Background
About Nitheesh Appala
I am Nitheesh Appala, a graduate student at PSU majoring in electrical and computer engineering. I completed my internship in the XEG2 team at Intel as a Physical Design Intern under Sanjay Balasubramanian's supervision where I Developed a TCL framework to automate the RF placements based on their slacks, worked on path profiling, and compared the Utilization, Congestion, Timing parameters before and after Clock tree synthesis for a high-performing block. I am very much interested in the VLSI domain and have done projects like TCL codes for getting the useless buffers and fixing timing issues. DRC and LVS checks for the FIFO design. RISC-V Simulator. Static timing analysis using primetime DMSA. UPF-based physical design for Hard IPs.
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