Noor Sarwar

Background

About Noor Sarwar

Experienced Semiconductor industry professional with 28 years of comprehensive expertise in Mixed Signal IP Design leadership, program management, customer support, and post-silicon debug and validation. Proven track record of delivering high-quality IP solutions, including DDR (LPDDR5, DDR5), TSV-based Wide IO, PLL/DLL, GPIO, and low power standard cell library. Results-driven Customer Support Engineer with extensive experience in mixed signal IPs, including DDR, HSIO, LDO, Die-to-Die Link, and GPIO. Provided technical support on pre-silicon IP integration, effective tracking/ resolving of IP issues, and collaborating with stakeholders to achieve high-volume manufacturing goals across multiple process nodes, including Intel 14nm, 10nm, i18A, and TSMC N3B. Seasoned semiconductor professional with Deep expertise in creating IP Design specification, Landing Zone, Integration Guide, Statement of Work (SOW), Circuit Architectural Spec and SoC/IP Integration Check list to guarantee high-quality designs that meet both technical and operational requirements for SoC and foundry customers. Experienced in low-power circuit design and power optimization at both the IP architecture and circuit levels. Proven track record of driving pre/post-silicon power correlation for hours of battery life (HOBL) and performance KPIs, ensuring efficient power management at a given bandwidth (data rate) for multiple generations of Intel client SoCs, including Alder Lake, Raptor Lake, Lunar Lake, Panther Lake, and next-gen developments.