Pascal Meier

Background

About Pascal Meier

Digital design engineer - SERDES link protocol (GMSL)- Functional Safety for automotive designs.> Functional Verification Engineer - SERDES for automotive applications- SOC verification platforms for embedded devices - Digital and mixed-signal verification for RF products >DFT Design/Verification Engineer - Lead design of scan for KNL microprocessor.> SERDES Design/Verification Engineer- Design and characterize high-speed serial I/O blocks using in CSI/PCIe.(PLL, TX Eq)- Design I/O control logic for analog PHY electrical signaling and bringup- Mixed-signal validation of training logic.> Physical Design Engineer - Floorplan, integrate, DRC and tapeout of analog test chips- Interface with board engineers on I/O placement, package design- Validation & testing of physical design tools for large microprocessor designs.