Patrick Fratta

Background

About Patrick Fratta

Patrick La Fratta completed his B.S. degree in Computer Engineering at Virginia Tech in 2003 and has accumulated work experience in industry, academia, and civil service for the U.S. Department of Defense (DoD). He completed his M.S. in Computer Engineering at Virginia Tech in 2005 with a thesis project involving extensive work in modeling and simulation in SystemC for the power and performance evaluation of a multithreaded, homogeneous multicore processor. He received his Ph.D. in Computer Science and Engineering in 2010 from the University of Notre Dame, where he conducted research in the areas of heterogeneous multicore processors, architectural extensions to the conventional memory hierarchy, and advanced multithreaded execution models. Following the completion of his Ph.D, Dr. La Fratta worked for the Aviation and Missile Research, Development, and Engineering Center (AMRDEC) under the DoD as a Science, Mathematics, and Research for Transformation (SMART) Scholar. He later joined the Architecture Development Group at Micron Technology with a concentration on the modeling and simulation of memory controllers. He is currently an HPC system architect at Samsung. His work in DRAM products has included hardware and software modeling and analysis of simulation data toward understanding the performance impacts of various system-level parameters. His development work has included the design and maintenance of software for an FPGA-accelerated processing system designed for genome sequence alignment using Smith-Waterman. He has authored and contributed to multiple patents in the areas of computer architecture and DRAM devices. His hardware experience includes extensive use of projection systems for photolithography as well as function generators and oscilloscopes for circuit analysis. His software experience includes the use of the GCC, Visual Studio, and various software evaluation environments including gem5, Sniper, SST, and OProfile.