Patrick Pereira
Asic Digital Designer, Sr Manager at Synopsys Inc
Based in Porto, Portugal
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Seniority
Other
Department
Other
Location
Porto
Industry
Software Development
Company size
28K
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p•••••••@synopsys.com
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Background
About Patrick Pereira
Fearless of the unknown. I have joined Synopsys in 2014 and I have been working on Mixed-signal designs that are implemented in sub-nanometer nodes. I am also part of:* Definition and implementation of digital blocks for mixed-signal IPs;* RTL development and verification. The hardware language description is Verilog. In verification, I have briefly worked with System Verilog under a UVM methodology.* Constraining multi-clock designs, static timing analysis, and scan insertion (stuck and asst);* Creation of behavioral models, based on analog schematics analysis to speed up the verification time;* Flow definition and scripts creation. Bash/tcsh, Makefile, Perl, TCL, and some Python;* From 2017 I have joined the Firmware team to today. 4+ years on hard/soft macros and Firmware for SERDES links like USB3.1/2, HDMI-TX, DP, D-PHY, M-PHY, and PCIe. 3+ years leading Firmware, from specification to verification.(CDR, AFEs, DFEs, TXEQs) 2+ years leading the FPGA work to validate those SERDES links (functionally).
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