Paul Kollaritsch
Staff Solutions Engineer - Ae at Cadence
Based in San Diego County, United States
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Seniority
Staff
Department
Information Technology
Location
San Diego County
Industry
Software Development
Company size
11K
Contact information
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p•••••••@cadence.com
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Background
About Paul Kollaritsch
6 Patents • 7 papers (including 2 best papers) • 1 book section • 1 award* Served on DARPA Design Automation steering committee* Patent “Programmable logic array interconnection matrix” fundamental patent for FPGAs* BEST PAPER: AI expert systems applied to chip design and implementation. “Cadre: A system of cooperating VLSI design experts,” B Ackland, PW Kollaritsch, et al, 1985 ICCD* Patent 8707228: “Method and system for implementing hierarchical prototyping of electronic designs.” FlexModel invention enables flat routing, budgeting, partitioning of 800M inst SoC in HOURS* AWARD: Production Innovation Award for FlexModel technology in Encounter Digital Implementation System, Cadence Design Systems 2011* BEST PAPER: “Plan to Success: Fast Big Chip Hierarchical Floorplan,” M Spohr, P Kollaritsch, cdnLIVE EMEA 2010* Patent 9760667: Allows timing in 1 sec of 800M inst SoC after moving a partition. “Method, system and computer program product for implementing prototyping and floorplanning of electronic circuit designs”* Patent 8719743: “Method and system for implementing clock tree prototyping”* Patent 10540470:"Generating a power grid for an integrated circuit", enables lines to compile to millions of Cadence Innovus commands to implement complex multi-power domain grids* Patent 10242145: Incremental power grid optimizer* Textbook section, VLSI Design: “A rule-based symbolic layout expert” (N Weste, 1984)* Paper: “Topologizer: An expert system translator of transistor connectivity to symbolic cell layout,” PW Kollaritsch, NHE Weste, 1985 Journal of Solid-State Circuits* Paper: “A unified design representation can work,” P Kollaritsch, et al, 1989 DAC* Paper: “CLAY: A malleable-cell multi-cell transistor matrix approach for CMOS layout synthesis,” P Kollaritsch, et al, 1988 ICCAD* Paper: “Circuit optimization techniques in DROID,” H Chen, P Kollaritsch, et al, 1991 Int’l Symposium on VLSI Technology, Systems, etc.* Paper: “Area evaluation metrics for transistor placement,” T Shiple, P Kollaritsch, et al, 1988 ICCD6
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