Pavan Shanbhag

Background

About Pavan Shanbhag

9+ Years of experience in ASIC Front end verification. Worked on functional coverage and code coverage. Worked on Power Analysis and Power Reductions techniques. Worked on Bringup of gatesim for prelayout and postlayout netlist. Worked on verification of Blocklevel verification using constrained random verification. Worked on OOPs based verification methodology. Worked on development of Testbench using HVL/HDL. Worked with team of 4 to 10 verification engineers based on the complexity of project. Managed the Block level verification activities. Key responsible for regression and documentation part. Hands on experience in Comprehensive Design Framework. Worked on simple regress scripts used for grid run and worked on regress fire on grid dedicated machines. Integration of components and bring up the environment for basic cycles. Developed environment components such as Data checkers, Trackers, Monitors and Functional coverage models. Report Status execution and tracking of project status till the closure. Excellent Debugging skills and failures at all stages of verification i.e, verif env development, component development, verification of the various blocks simulations. Worked on revision control systems CVS,SVN,GIT and BOM gallery. Worked on Block Level and Chip Level Verification. Worked on Emulation - Quickturn. Specialties: Excellent knowledge of Verilog/VHDL/Vera/Perl/Tck/SV. VMM/RVM/OVM methodologies. Excellent working knowledge of simulator tools - Power Theatre, PA, PowerPro, Verdi, Explorer, Mpsim, Synopsys VCS, DVE, Debussy,@Verifier,@Designer, XeDebug, PXP etc. Hands on experience in writing Makefile. Worked on the verification of protocols such as PCI Express Gen1/Gen2/Gen3 mode of PHY layer. Developed environment which involves third party verification IPs. Developed the functional coverage models.