Peter Janssen

Background

About Peter Janssen

HW System Engineer with 10+ years experience in SOC/ASIC/Subsystems verification using FPGA prototyping systems. Experience areas: • HW System Architect of the ARC Software development platforms (AXS/HSDK) • Designing and building ARC based demonstrators • PCB design (simple designs) using Eagle • PCB design Specification (Specification PCB designs of Prototyping boards / Systems, Outsourcing PCB Schematic Entry and Layout, Involved in review process, Board bring-up / Board Validation) • Debugging broken software development platforms • Lab experience (soldering, logic analyzers, clock generators, Oscilloscopes, microscopes, wafer probers) • Altera / Xilinx based FPGA tool flow (Synplify_Pro, Synplify_Premier, Identify, ISE, Vivado, QuartusII, Precision, ChipScope ) • Mapping ASIC SOC design onto FPGA (Mapping SOCs with ARC/ARM/MIPS CPU’s with several Interface IP (SPI, UART IIS, SPDIF, IIC, Ethernet, USB etc.) and Memory controllers onto FPGA’s. Some experience using Synopsys Core tools / DesignWare IP) • Building top level CPU centric FPGA designs (VHDL, Verilog, System Verilog) • Experience with advanced FPGA Prototyping systems (ARC HSDK, ARC AXS, HAPS5, HAPS7, HAPS-DX, HAPS80, EMSK, ASCOT prototyping system, ARM ReaLview) • CPU Debugger experience (Metaware debugger, Realview) • Scripting (A working understanding on scripting, programming, test-benches, system design and experience in debugging) • Working in a High Tech Environment (Complex EBPG’s, X-Ray systems) • ASIC Design/Test knowledge (as VLSI Test Engineer, IC characterization, Diagnostics) • Documentation (User guides, Technical notes, Web sites, sharepoints)