Peter Li
Sr Soc Physical Design Engineer at Samsung Electronics America
Based in San Jose, United States
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Seniority
Staff
Department
Engineering
Location
San Jose
Industry
Computers and Electronics Manufacturing
Company size
10K
Contact information
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p•••••••@••••••.com
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Background
About Peter Li
Executive and passionate Silicon Valley professional in ASIC physical design leader with expertise in all facets of high speed, high gate density and high pin count chip design, complete ASIC physical design flow from RTL to tape out, RP and customized macro design. TSMC N16, N10 and beyond advanced tech nodes within high-profile corporations. Skilled in collaborating with all members of the organization to achieve business and financial objectives. Instrumental in streamlining and improving processes, enhancing productivity, and implementing technology solutions. Technical Proficiency in Synopsys DCG, ICC, ICC2, ICV, StarRc and PT, Cadence synthesis and ATPG.
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