Prabhat Yadav

Background

About Prabhat Yadav

Worked on AXI4 protocol & micro-architecture design for AXI interface and AXI -Pipeline for HBM4 memory controller-Design understanding of HBM3/4 DRAM Memory Architecture -Different HBM memory densities,On-chip error detection/correction mechanisms using verilog - Worked on different ASIC Front-end design/Verification genAI tools bring up & validation for different IPs-knowledge of lint, RDC & CDC-Worked in Design & Creation of Packages for RMMI, MIPI M-PHY IP-HDL(Verilog & System Verilog), STA & Digital Electronics knowledge. •Shell/Perl ScriptingExperience:•Worked on High -Level Synthesis using C++(catapult), Debugging RTL, Estimation of QoRs, Analysis of different suites in Regression, Makefile, Creation of Testcases for replication of Customer's Issues, Pre & Post Synthesis.•Trained in Design Verification using System Verilog (Semi-Design).Previous Experience - ETL Developer, SQL developer, worked as Linux Admin,Worked in Shell India pvt.ltd IT Centre.