Pranay Kumar

Background

About Pranay Kumar

I'm Pranay Kumar Kola, an ambitious graduate student in Electrical Engineering at San Jose State University, with a passion for the intricate world of VLSI. A blend of creativity and technology has fueled my journey, and I am eager to contribute to the ever-evolving field of VLSI circuit design. My expertise lies in the fascinating realm of FPGA and ASIC development, where I bring digital circuits to life using RTL and SystemVerilog. With a keen eye for detail, I excel in testbench development, ensuring thorough functional verification and coverage-driven verification. I possess proficient skills in debugging and simulation, boldly tackling challenges to ensure the reliability of my designs. Key Highlights: Top skills ->Core Skills: Computer Architecture, Computer Organization, RTL Design and Verification, Digital Logic Design, SRAM, Logic Verification, Object Oriented Programming, Code Coverage, Static Timing Analysis, System Verilog assertions, UVM->EDA Tools: Model Sim, Questa Sim, Quartus Prime, Synopsys VCS, Synopsys Verdi, Xilinx Vivado->Hardware Descriptive Language: Verilog, System Verilog, MIPS Assembly Language->Operating System: Windows and Linux->Programming Languages: C, Python. Project->Implementation of Image Processing Functions on PYNQ FPGA ->Cache Simulator ->MIPS ISA Dot Product with Forward Chaining -> Router 1X3 - design and verification using Verilog Behavioral skills -> Adaptability -> Teamwork -> Collaborative ->Problem-Solving