Praneetha Nalluri

Background

About Praneetha Nalluri

As a highly motivated Master's graduate in Electrical and Computer Engineering from Colorado State University, I am seeking a challenging role as a Verification Engineer or Validation Engineer in the VLSI domain. My academic background, coupled with hands-on project experience, has equipped me with a robust understanding of VLSI system design, digital signal processing, and embedded machine learning. During my studies, I have undertaken various projects that demonstrate my ability to design, analyze, and optimize complex digital systems. For instance, I designed an 8-bit synchronous counter using Cadence Virtuoso, optimizing it for high-speed applications and energy efficiency. Additionally, my work on the performance analysis of optical interconnects using Synopsys RSoft resulted in significant improvements in signal loss and data transfer rates, showcasing my proficiency in optimizing high-performance computing systems. My technical skills span a wide range of tools and languages essential for VLSI design and verification, including SystemVerilog UVM, Verilog, VHDL, Cadence Virtuoso, Synopsys RSoft, and OrCAD PSpice. I am adept at RTL design, testbench development, and verification planning, with a strong foundation in computer architecture and debugging. With a strong academic record and a proven track record of successful projects, I am eager to contribute my expertise to a forward-thinking organization in the semiconductor industry. I am passionate about leveraging my skills to drive innovation and excellence in VLSI design and verification.