Probil Kumar

Background

About Probil Kumar

Worked on LTE PHY Baseband block where we developed and enhanced the testbench environment using System Verilog and Universal Verification Methodology (UVM). Created the UVM infrastructure for verification of a Serial Peripheral Interface, OBSAI and JESD etc. which include uvm_env, uvm_scoreboard, uvm_driver, etc. Verified the 10ms frame of LTE for both uplink and downlink. Created the BFM for OBSAI and JESD which include transmission and reception of frame packets. Major features: • Transmission of messages for 4 different antenna depending upon the destination address present on header byte • State machines for obsai framer and deframer and sync up to the 10 ms pulse by transmitting k28.5 and 28.7 character. • 32 bit Scrambler and descrambler for 6.144Gbps link. • FIFO array to create a payload of 128 bit to a prescribed address. • Reception of data packets and store to separate file for each antenna. • Transmission of tones at frequency of 30.72Mbps to verify the low pass filter present on in the baseband Created test cases for different sub-blocks like SPI, UART, TDD etc and different scenarios. Filed bug reports, verified RTL fixes, analyzed test results and performed coverage analysis. Wrote Python script to test the output data and generate the simulation result. Designed the timing constraint (SDC) for PCIe and OBSAI and provided the solution for timing failures.