Quan Dang

Background

About Quan Dang

Accomplished Analog/ Digital Mask Designer experienced in all stages of design cycle from Initial Layout Design specification to Tape-out final product PRQ of different High-Speed SerDes Analog/Mixed-Signal I/O interfaces.• A key layout contributor/expert in major Server design groups that designed I/O interfaces like DDR, GDDR, PCI-E, and HBMIO generations for successful products with CMOS process nodes from 250nm down to 14nm, 10 nm FinFET.• Deep experience with full custom CMOS layout floor-planning from Top down (from Bump to transistor level) with multiple robust power domain distribution grids up to TM1, delivering bottoms up from transistors to bump integration.• Custom layout expertise in the design of Analog/ Mixed Signal High Speed blocks like: Transmitter, Receiver, ESD, Thermal Sensor, Op-Amp, Bandgap, Clock Spine, VCO, PLL, DAC with layout techniques: Matching different pairs, common centroid, dummy devices, matching, critical signal routing shielding, and antenna and noise isolation.• Detail oriented: Layout with RV, IR drop, RC delay, noise, latch-up and DFM awareness to minimize the future fixes.• Layout design Tools: Cadence Virtuoso XL, Cadence Virtuoso Schematic Composer, Genesys/Gena (Intel tools).• Verification Tools: DRC, LVS, ERC, Antenna, DFM and ESD checks Mentor Calibre, RVCAT.• Others: UNIX, Linux, common use of Perl, Tcl, MS office (Excel, PowerPoint, Word).• Excellent communication in working with large functional DE and MD teams across sites, domestic and internationally.• Strong team player and leader. Able to estimate layout dimensions, time schedule for each IP blocks, fubs. Train and mentor junior mask designers to deliver and meet dead line milestone requirements without compromise quality.• Quickly learn & adapt to updated technology & IC layout applications. Creative, flexible, discipline & self-motivated.