Razvan Cercel
Physical Design Team Leader at Capgemini Engineering
Based in Braşov, Romania
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Seniority
Manager
Department
Engineering
Location
Braşov
Industry
Engineering Services
Company size
45K
Contact information
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r•••••••@••••••.com
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Background
About Razvan Cercel
Versatile and results-driven Senior Physical Design Engineer with many years of experience in the semiconductor industry. My experience includes everything from RTL to signoff tasks, with a proven track record of tapeouts in Structure ASIC technology up to 16nm. Strong knowledge in integrated circuit design: RTL design (Verilog/SVerilog/VHDL), simulation, timing constraints (SDC), synthesis, P&R, gate level simulation, formal verification, timing analysis, ECO. Strong knowledge in working with EDA tools: Synopsys suite: Design Compiler, Fusion Compiler, StarRCXT, PrimeTime, LynxNXT, Formality, VCS Cadence suite: Genus, Innovus, Tempus, Conformal LEC, Incisive/Xcelium Mentor suite: Tessent, Questasim
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