Rishabh Jangid

Background

About Rishabh Jangid

M. Tech Projects: CADENCE VIRTUOSO 1. Design the layout of 8x8 SRAM Array using gpdk 180nm technology node- Low Power Design techniques are used so as to reduce average power dissipation to 109 uW. Design the layout of Master - Slave D – Flip Flop using 2x1 MUX using gpdk 180nm technology node- Post Layout Simulation is performed which shows the result of propagation delay as 25.623 ns. XILINX VIVADO 1. Interfacing VGA with Basys3 FPGA to display “NO SIGNAL” Screen using Verilog- The standard 640 x 480 resolution “NO SIGNAL” screen is displayed on monitor screen- Total On-Chip power consumption = 0.074W out of which static power = 0.072W and dynamic power = 0.002W. Vending Machine using Verilog- The Vending Machine consists of 4 different items of different cost. Four different module is designed for four different items and a top module is there above of all of these four modules- Item is dispensed if the coins value entered is equal or more than the cost of the item. If coins value is greater than item cost then exchange is given back- Testbench is written to verify the functionality. Traffic Light Controller using Verilog - FSM based system is designed to control the traffic light at junction point of two roads- The green light of the main road is ON for most of the time except there is some vehicle on the other road waiting to cross the main road- Testbench is written to verify the functionality.