Ritika Modi

Background

About Ritika Modi

I’m a VLSI Design & Integration Engineer with over 6 years of experience working across RTL integration, power-aware design (UPF, VCLP), synthesis, and formal equivalence checking using Synopsys tools. I've worked hands-on with complex SoC designs, owning the integration and clean synthesis of 20+ partitions, while ensuring dangle-free connections, automation in flow setup, and debugging non-equivalence issues across RTL and gate levels. In my early career, I implemented protocol-level RTL (Ethernet, SPI) for thermal imaging systems and contributed to memory interfacing and dynamic calibration logic. I’ve also led teams and collaborated with CAD, PD, and synthesis engineers to streamline design workflows. I’m currently expanding my skillset with an AI/ML course from IIT Ropar, aiming to bridge traditional SoC design with emerging AI-driven workflows. I’m actively exploring product-based roles where I can drive impactful silicon design work from spec to sign-off. Areas of focus: RTL Integration • Low Power Design • Formal Verification • Verilog/SystemVerilog • Synthesis (Fusion Compiler) • Protocols (SPI, Ethernet) • ASIC Flow Debugging • AI/ML-in-Hardware (Learning Phase) Let’s connect if you’re working on advanced SoC design, AI hardware, or are looking for engineers with real passion for design closure and innovation!