Rohan Rajesh

Background

About Rohan Rajesh

An VLSI Enthusiast always looking to gain knowledge and acquiring skills to achieve great heights in VLSI industry/world. Currently working on TSMC N2P UCIE Project (2 nm)(Worked on Vreg(Voltage Regulator) Library, developed FP of Vreg_ato,Vreg_ls and Vreg_ctrlwrap cells with cleaned tapeout Verifications.Also created LEF for Vreg Lib.) Worked on 18a LVDS Project (Created Rx top cell for H/V version, also worked on sub-cells of Rx and Tx cells with cleaned tapeout Verifications like DRC,LVS,MHV runs along with EMIR and PERC runs. Also created ALLCELL and ABUTMENT cells and done respective tapeout Verifications.) Worked on 22nm icf Intel (Worked on the Pre-Driver, CDM and HBM cells, With Physical Verifications ). Worked on 22nm FDX project GlobalFoundries (Worked on Control-logic and Wpupd cells with placement and floor planning. Good debugging skill for leaf-cell/instance level DRC and leaf-cell level LVS. Worked on other Physical Verification Such as DRC, LVS, RC-Extraction, MQA, PERC, etc ) along with RC Extraction and Multistack Verifications Checks. Hands on in PV fixing for following checks DRC, ERC,LVS etc. Responsible for different leaf Cells layout development with following steps like floor planning, placement, routing, followed by Physical Verification checks at Instance levels Good understanding and working experience on EDA tools like Virtuoso, Calibre, Custom Compiler, ICV. Basic Concepts of, Scripting languages like Unix. Having a good experience on 180nm to 45nm.