Saida Akhter
Senior Design Engineer at Cadence
Based in Portland, United States
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Seniority
Staff
Department
Engineering
Location
Portland
Industry
Software Development
Company size
12K
Contact information
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s•••••••@cadence.com
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Background
About Saida Akhter
Senior Physical Design Engineer working on advanced technology node. Work includes full ASIC flow, starting from Floorplan to sign-off. Tools include Cadence Innovus, Tempus.HDLVerilog, SystemVerilog, VHDLLANGUAGESPython, TCL, C, C++TOOLSSynopsys Design CompilerSynopsys IC CompilerSynopsys PrimeTimeVLSI Magic and HSpiceMentor Graphics Questa SIMMentor Graphics Questa PropCheckXilinx VivadoTI Code Composer StudioNI LabVIEWCONCEPTSStatic Timing Analysis ( STA )Unified Power Format ( UPF )SystemVerilog Assertions ( SVA )Synthesis to Sign-off || Netlist to GDS II
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