Saikumar Rapeti

Background

About Saikumar Rapeti

Analog Design Engineer working in the semiconductors industry experience in designing PLL sub blocks such as PFD, Charge Pump, Lock Detector, Bias Generation Circuits, Single/Two Stage Differential amplifier, Supply Filter and Clocking sub blocks such as Custom Flip-Flop, High-Speed Dividers, Pre PI-Buffers, Post PI Buffers, Common to IO Buffers, RC based Delay Unit(PBD) for high speed SERDES IPs Good Understanding of fundamentals of Analog Integrated Circuit Design, Analog Circuits, Semiconductor Device Physics and Digital Circuit Design Experienced in design, simulation, post-layout extraction, and verification with Cadence and Synopsys Full Custom Tools and having exposure to advanced technology nodes (TSMC 5nm/12nm) Familiar with Circuit Reliability Simulations such as- Across Process/Voltage/Temperature (PVT)- Electromigration and Interconnect Reliability (EMIR)- Monte Carlo - Aging and Electrical Over Stress Designed a Programmable Drain Switching Charge Pump for PLL application in TSMC 12nm Designed a single stage Operational amplifier for Charge Pump application used inside PLL in TSMC 12nm Designed a PLL Lock Detector to check the locking condition of the PLL in TSMC 12nm Designed Supply Filter, Current mirror Circuits, Bias generation Circuits for PLL application in TSMC 12nm Have an initial strong hands-on experience on PFD design(PLL Application), Two stage Operational Amplifier design(DAC Application) and assisted to the team to Perform PLL top level simulations Designed a high speed (8GHz) differential and single ended custom flip flop, with reset functionality Designed a high speed RC based Delay unit with 0.5p LSB (at Fastest PVT) for PerBitDeskew application