Sam Choi

Background

About Sam Choi

Keenly curious and team building expert in Interconnect technology integration, process development, and reliability. CMOS development and MFG experiences from 130nm to 7nm technology nodes. Deep and broad skills in CMOS processes such as film deposition, lithography, metallization, CMP, WET, and especially RIE. Practiced experiences to identify root cause from electrical signals to physical fails and recommend best practice solutions. Recent experience in FEOL Contact integration at 7nm node.* Multiple years of working in a manufacturing and research groups to drive innovate ideas from concept to manufacturability; identified issues and resolutions for proof of concept integrations, YIELD ramp, and increase capacity.* Highly skilled with both 300mm FAB Manufacturing and research methodologies in FMEA, 8D, capacity, cycletime, Cp/Cpk, control charts. Experience with numerous physical and analytical characterization tools data analysis, i.e, TEM, XPS, FTIR, Auger, EELS, Raman to appropriately identify techniques to understand failures.* Leadership experience as lead 14nm node BEOL integrator and BEOL RIE team leader. Experience working with designers, device engineers, and electrical characterization engineers. Ability to articulate ideas and issues to broad audiences from executive management to technicians.* Experience with Compound semiconductor laser diode processing * Granted 38 US Patents in Si CMOS technology and contributor of published articles.* Many years of experience working in a diverse environment and multi-cultural engineering team from Japan, South Korea, Europe, and China.