Verified recordHigher Education

Samar Saha

Adjunct Faculty at Santa Clara University

Based in Milpitas, United States

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Seniority

Staff

Department

Education

Location

Milpitas

Industry

Higher Education

Company size

4.9K

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Email

1 credit

s•••••••@scu.edu

Phone

5 credits

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Background

About Samar Saha

An internationally recognized expert on IC device architecture, process/device simulation, and device modeling within the industry and academia. For over last 35 years, worked on process and device architecture of silicon microelectronic devices including CMOS, Bipolar, BiCMOS, split-gate flash memory cells, JFET, and HV-LDMOS (BCD technology). Acquired wide experiences through working for multinational integrated device manufacturers (IDMs), Fabless companies, Electronic Design Automation (EDA) companies, and semiconductor foundry; widely interacted with semiconductor foundries. Extensive work experience of using technology CAD (TCAD) and device modeling tools for process/device architecture and device characterization. Graduate and undergraduate teaching experience in VLSI process/device physics over 20 years.Authored more than 100 research papers, FOUR Books including two (sole-authored):(1) FinFET Devices for VLSI Circuits and Systems, CRC Press (2020) and (2) Compact Models for Integrated Circuit Design: Conventional Transistors and Beyond, CRC Press,(2015) and two co-edited:(3) 75th Anniversary of the Transistor, John Wiley & Sons (2023) and (4) Micro and Nanoelectronics Devices, Circuits and Systems, Springer (2023); and one Book Chapter on TCAD, entitled, “Introduction to Technology Computer-Aided Design,” in Technology Computer Aided Design: Simulation for VLSI MOSFET, C.K. Sarkar (ed.), CRC Press,(2013); and holds 13 US patents (on nanoscale MOSFET, BiCMOS, and JFET device/process architecture and flash memory sensing). His "Book (1) on FinFET" has been translated in Chinese language and published in 2022.Actively involved in activities: 2016-2017 President of the Electron Devices Society (EDS); served as the head guest editor for the TRANSACTIONS ON ELECTRON DEVICES (T-ED) Special Issues (SIs) on “Advanced Compact Models and 45-nm Modeling Challenges” and “Compact Interconnect Models for Giga Scale Integration;” and as a guest editor for the T-ED SI on “Advanced Modeling of Power Devices and their Applications.” Specialties: TCAD (2D/3D simulation), compact modeling (MOSFETs, FinFETs, BJTs, TFETs), bulk and thin-body FETs, nonvolatile (split-gate flash) memory process/device architecture and exploratory device architecture and characterization.

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