Samrat Patel

Background

About Samrat Patel

Around 10 years of experience in Functional verification and target (hardware) level verification of the design. • Development of Verification Environment/Verification Component/UVCs using System Verilog with UVM Methodology • Extensively worked on DO-254 DAL-A projects starting from requirement review to results closure. • Involved in writing comprehensive detailed VCD (Verification Case Document), VPRD (Verification Procedure and Result Documents), for Functional Simulation, Target (HW) testing and Analysis methods in FPGA level verification. • Experience in developing test bench compliant to DO-254 using System Verilog and UVM for functional simulation testing of DAL-A FPGAs. • Good hands on closer of 100% functional and code coverage for DAL-A FPGA. • Experience in identifying testing method (Simulation/Hardware/Analysis) of each requirement. • Experience in creating/reviewing complete traceability from requirements->VCD->VPRD->Results using IBM DOORs tool. • Development of Verification Test Procedures for hardware level testing. • Good experience in verifying DMDA level/Low level with small internal timings requirements. • DMDA level of requirement verification for Digital Signal Processing (DSP) component like IIR-Filter, Limiter, CORDIC cartesian to polar, Multiplier, divider etc. • Involved in PR(Problem Report)/CR(Change Request) process for DAL-A device, with complete impact analysis to all the verification artifacts and requirements. • Involved in configuration management and complete detailed review using tool like Synergy and DOORs. • Experience in performing Dry and Formal runs (RFS). • Graphics Processor Post-Si Validation. • Managing team and guiding them for project execution/development. • DO-254 Standard Process/Configuration Management and Process Compliance Documentation • Multiple DO-254 SOI#3 Audits Involvement and closer with zero findings. Domain: ASIC/FPGA Verification Technology: Avionics FPGA, SOC Verification Methodology: UVM HVL: System Verilog HDL: Verilog Protocol knowledge: ARINC 429, AXI4, EADIN, A2D, D2A, DDR2, EMIB MDFIS (DIE2DIE PHY) Process Knowledge : DO-254 DAL-A Known Languages: C, C++ EDA Tools: Perforce, Synopsys VCS, Questasim, CVS, SVN, DOORS, PREP Scripting: Working knowledge of PERL, Shell, Makefile Operating Systems: Linux, Windows