Sanjay Patel
Senior Pre-silicon Verification Lead at Intel Corporation
Based in Folsom, United States
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Seniority
Manager
Department
Engineering
Location
Folsom
Industry
Semiconductor Manufacturing
Company size
110K
Contact information
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s•••••••@intel.com
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Background
About Sanjay Patel
Accomplished Senior Pre-Silicon Verification Lead with 13+ years of experience in the semiconductor industry. Proficient in developing and debugging UVM and System Verilog based test environments. Expert in crafting comprehensive functional verification test plans. Successfully led verification teams delivering a range of client chipset products (Sunrise Point, Cannon Lake, Tiger Lake, Meteor Lake, Lunar Lake) for desktop, mobile, and automotive markets. Demonstrated ability to optimize verification efficiency through automation, reducing regression and coverage collection time. Experienced in SoC integration and post-silicon debug support: Technical Skills - Verification Languages: UVM/OVM, SystemVerilog, Verilog, VHDL. Scripting Languages: Perl, Shell, Tcl, Make, VimScript. Other Languages: C, C++, ASM. Protocols expertise: AMBA AHB/AXI/APB/LP (ARM/ARC), PCI, PCI-Express, SPI/eSPI interfaces. Tools/Packages: Xilinx ISE, Synopsis VCS, PrimeTime, Modelsim, L-Edit,(G)Vim expert. OS: Windows, Unix, Macintosh.
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