Sarthak Vedpathak
Dft Engineer Trainee at Chipedge
Based in Pune, India
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Seniority
Staff
Department
Engineering
Location
Pune
Industry
Semiconductor Manufacturing
Company size
236
Contact information
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s•••••••@chipedge.com
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Background
About Sarthak Vedpathak
As a DFT Engineer Trainee, I possess a strong understanding of ASIC Flow and DFT Fundamentals, including SCAN Design, SCAN DRC, SCAN Insertion, SCAN Compression, Boundary SCAN, JTAG, ATPG Faults, Fault Models, ATPG Coverage, and Pattern Simulation. My skills in these areas allow me to develop efficient and effective SCAN architectures for modern ASIC designs and create effective test patterns that ensure high levels of fault coverage for both Stuck-at and Transition fault models. Overall, I am a highly motivated and dedicated trainee with a passion for semiconductor design and testing. I am committed to learning and growing my expertise in these areas and would be a valuable addition to any organization looking for a skilled and enthusiastic team member.
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