Saurav Dutt

Background

About Saurav Dutt

Design For Test (VLSI Engineer). Currently working for Advanced Micro devices DFT CAD team Nature of Work- I am part of the central DFX CAD team. I mainly architect and develop flows for Scan/Atpg @ both IP/SOC level. I have good understanding of DFT and Clock Architecture. In tessent, I am familiar with IJAG, SSN, ICL/PDL, EDT IP insertion, ATPG, advanced fault models like cells aware, bridging faults, cell neighborhood faults etc. I also assist the SOC ATPG team in silicon failure analysis using tessent tools that are observed during scan tests. In the past I have worked with Synopsys TMAX and Cadence ATPG tools too. I have a good understand of primetime (Static timing analysis) and also assist SOC DFT teams with STA constraints and exceptions for DFT modes. I am familiar with the following standards- IEE1500 & 1687. Recent Projects- 1> Lead a small team to develop Fusion Compiler Binary Flow for Scan Insertion. I was the main architect/developer of the flow. Coordinated with Synthesis and Physical design teams and deployed the new flow to the SOC team. I also delegated tasks and mentored junior team members. Some of the salient features of the flow are- a> Binary file (ndm) transfer b/w different stages. b> Improved scan partition, power aware & upf handling and insertion of Isolation/LS cells. c> TE hookup of clock gating cells. d> Test Point insertion improvement. e> Memory and latch array sub chain stitching. f> Better QOR results from PPA perspective compared to the existing flow. g> Developed a robust flow to minimize maintenance and support. i> Automated to minimize manual effort. 2> Lead a small team to develop SOC level ATPG Flow. This flow was developed to drive convergence, improve efficiency, increase reliability and adoption of a standardized SOC ATPG flow across the organization. Some of the salient features of the flow are- a> The flow translates/merges IP/block level ATPG patterns to the SOC level and verifies the same. b> The flow supports translation for identical cores and accelerated flyover which are strategies to minimize the scan channel requirements at the SOC level. c> The flow ensures reliable file transfer b/w IP/block level and SOC level. d> The flow supports translation of Chiplet level patterns to package level and also supports on-die scan comparator mode. e> Checkers to incorporated in the flow to ensure that test-data registers are configured correctly during ATPG. Programming Languages :Hardware (Verilog). Shell Scripting (Perl, tcl, shell scripting) SW Programming Languages(C, Python).