Savvas Sgourenas

Background

About Savvas Sgourenas

Born in Athens, Greece in 1975. Received Dipl. Eng. degree from the School of Electrical and Computer Engineering of the National Technical University of Athens (NTUA) in In the past 18 years worked as a designer and project leader in various companies situated in Greece, UK, Netherlands, Switzerland, France, Germany & USA. Current responsibilities include team management, architecture lead for Frequency Synthesizers and High-Speed SERDES integrated systems, project planning and mentoring. The architecture and system definition of High-Speed interface transceivers, PLLs as well as the design of Analogue Mixed-Signal and RF integrated circuits is main area of expertise. Experience accumulated/ technical skills developed throughout career, include the following: • Project/Technical leading for Frequency Synthesizers for Wireless Transceivers • Project/Technical leading for Wireless and SerDes Transceivers • Architecture definition / system specification for Fractional-N/Spread Spectrum/Integer-N PLLs for High Speed & Wireless Transceivers • Architecture definition for Wi-Fi Wireless Transceivers • Architecture definition for SERDES Transmitters/Receivers • Multi Gigabit High Speed interfaces experience include DDR4, USB4, PCIe, M-PHY, Display Port • High Speed CTLEs, Phase Interpolators, CDR loops • High Speed Drivers, Equalizers, Serializers, Duty Cycle correctors, Calibration loops • RF circuitry design i.e. VGAs, Mixers, RF amplifiers, Power detectors, RSSI • DC-Offset loops / Analogue Loop-backs • ΣΔ. ADC, SAR ADC converters / DACs – Calibrations loops, Digital Error Correction • Multi-phase carrier generation architecture definition, system design, modelling for Phased-Arrays • Coupled PLL arrays for Phased-Arrays, RF phase detectors, Phase shift loops, RF drivers • PLL System design / modelling / top-down specifications definition (Integer-N, Fractional-N, Spread-Spectrum) • PLL Calibration algorithms architecture & design • PLL Charge-Pumps, Phase-Detectors, XTAL design • LC, Ring, Injection locked Oscillator design • High frequency Dividers/Prescaler/Fractional-Divider design • Architecture definition / system specification for DLLs • Mixed-Signal, Verilog-AMS, System-Verilog modelling & Verification • ASIC digital design flow