Stefan Stojicic

Background

About Stefan Stojicic

Graduating from the School of Electrical Engineering in Belgrade, Serbia, I have established myself in the semiconductor industry as a Design Verification Engineer. My expertise lies in both functional and formal verification, where I utilize SystemVerilog and UVM to ensure the highest standards of product development.In my current role, I apply my understanding of semiconductor design processes to effectively verify complex systems, consistently ensuring accuracy, efficiency and functional integrity in product performance. My proficiency in scripting language like Python enhances my capability, particularly in automation tasks, which streamlines processes and improves productivity.I am passionate about the ever-evolving world of semiconductor technology and thrive on the challenges it presents. My goal is to utilize my expertise in design verification and my passion for cutting-edge technologies to drive innovation and efficiency in this rapidly evolving field.