Steve Nease
Senior Digital Design Engineer at Btq
Based in United States
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Seniority
Staff
Department
Information Technology
Location
United States
Industry
Semiconductor Manufacturing
Company size
35
Contact information
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s•••••••@btq.com
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Background
About Steve Nease
ASIC chip lead and design/verification engineer with experience leading advanced-node tapeouts. Proven ability to optimize design and verification flows to improve design time and QoR. Experienced with a wide array of VLSI methodologies: RTL-to-GDS, AMS, UVM, and flow automation.
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